Several bus technologies have been developed for communication between electronic devices, management of electronic devices, or both, particularly components used in computer architectures. For example, the Industry Standard Architecture (ISA) bus was used to connect a microprocessor to system resources such as memory, input/output ports, and video controllers. Over the years, advances have been made in bus architectures allowing faster access, an increased number of devices supported, and higher data throughput. Examples of faster architectures are the Enhanced ISA (EISA), micro channel architecture, and Vesa bus. A later contender in this arena is the peripheral interconnect (PCI) bus, a parallel architecture, originally with a 32-bit channel width and a 33 MHz clock speed. Later revisions allowed wider paths and higher bus speeds.
However, wide buses such as PCI can be difficult to route on a circuit board and wide, high clock-rate busses can propagate clock noise. As a result, the PCI bus reached a performance limit. As packet technology has developed, a new bus architecture arose around packet-based transport using serial interconnects, or lanes, rather than parallel bus architectures. Examples of packet-based bus architectures include Peripheral Component Interconnect Express (PCIe), Hypertransport, Infiniband, and RapidIO.
Another advantage of newer packet-based bus architectures involves higher protocol layers of the bus architecture that support robust signaling for acknowledgement, polling, interrupts, etc. However, the physical implementations of such busses can limit the useful distance over which such architectures are useful. For example, the PCIe version 1.0 bus has a limit of 20 inches between devices.